1. Field of the Invention
The present invention relates to an etching method for forming a via hole or interconnection groove in a low-k film (an insulating film having a low dielectric constant) used in a multilayer interconnection structure of a semiconductor integrated circuit, and to a semiconductor device fabricating method using this etching method.
2. Description of the Related Art
In recent years, as the miniaturization of semiconductor devices advance, the importance of multilayer interconnection technology has been increasing in addition to the importance of the miniaturization of transistors. Additionally, it is becoming increasingly important to reduce interconnect delay in multilayer interconnection. As one method of reducing interconnect delay in multilayer interconnection, it is known that a low-k film can be effectively used in place of the oxidation film that has been used up to this point as an interlayer insulating film.
However, in a case where a low-k film (here, an organic SOG film) is used as an interlayer insulating film, the etching shape of a hole pattern bottom portion changes to a shape called a trench where etching speeds at the center and at the end of a pattern greatly differ.
In this trench, since etching progresses more rapidly at the bottom end of a pattern than at the center of the pattern, it is difficult to stop the etching at a desired depth even if an etch stop layer is used. For this reason, problems arise in that, at the pattern end portion where the etching speed is high, the etch stop layer is pierced and underlayer interconnection (e.g., copper interconnection) is exposed to plasma, and in an etching condition including oxygen, the surface of the copper interconnection is oxidized and contact resistance rises.
In addition, because the trench of the pattern bottom portion forms minute slits, these slit portions may not be covered by a barrier film such as Ta and TaN used as a copper diffusion-preventing film. When portions not covered by the barrier film are present, copper diffuses from those portions, which can cause a short circuit with adjacent interconnection and exert a large influence on transistor properties (see M. Mizumura et al., JJAP, Vol. 41, pp. 425–427; and S. Uno et al., Proc. of Dry Process Symp., pp. 215–220 (1999)).
In order to solve this problem, Japanese Patent Application Laid-Open Publication (JP-A) No. 2001-077086 discloses an etching method where the mixing ratio (O2/(C4F8+O2)) of a mixed gas of C4F8 and O2 serving as an etching gas is controlled, the etching speed of an organic SOG film is improved and the etching shape (via hole shape) of a hole pattern bottom portion is stabilized.
In JP-A 2001-077086, a stable etching shape (via hole shape) of the hole pattern bottom portion can be created. However, technical demands of recent years continue to escalate. Moreover, the current state of affairs is one in which improvements are being anticipated.